Over the past decade, defect inspection to detect microscopic manufacturing defects has become a standard part of micro-fabrication manufacturing flows, especially for semiconductor wafers.
Each type of inspection technology is usually applied at steps in the semiconductor manufacturing flow where it is best suited to the types of defects most likely to be found. The economic benefits of inspection have been substantial and inspection is generally accepted as having made a significant contribution to the substantial increase in semiconductor wafer manufacturing yields seen in the 1990s.
Inspection systems are employed in a number of different applications including: process monitoring to flag when a particular process step in the manufacturing flow has an increased defect density above the level normally expected at that step; problem solving by inspecting so-called short-loop wafers that have only been processed with a subset of the manufacturing process steps in order to facilitate troubleshooting and diagnosis or optimization of a particular subset of process steps and during process development in order to optimize a new manufacturing process to reduce or eliminate process-specific or systematic defect mechanisms.
Wafer inspection systems for patterned wafer inspection usually work as follows. A high powered microscope, traditionally an optical microscope, but more recently a SEM (Scanning Electron Microscope) or electron microscope, is set up under computer control to acquire sequentially images of the area of objects such as a wafer that include multiple integrated circuits that are arranged in dice, masks or reticles for micro-fabrication, flat panel displays, micro-electromechanical (MEMs) devices and the like during and after manufacture.
The image or contrast data that is acquired in this manner is then compared to reference data. Defects are found or detected where there are differences between the reference and the acquired images. The reference images may be derived from Computer Aided Design data as is often the case with mask or reticle inspection. Additionally or alternatively, the reference images may simply be images of neighboring cells or die on the wafer or similar wafer being inspected. The sensitivity of the defect inspection process to small defects can be controlled by adjusting the image acquisition parameters such as pixel size, contrast, brightness, charging and bias conditions etc., and image processing parameters that are used to compare the acquired inspection images and reference images.
An object such as a wafer can include repetitive regions that include many repetitive structural elements such as memory cells (such as SRAM, DRAM, FRAM, Flash memory). Repetitive regions can also include repetitive structural elements programmable logic cells such as those included in PLAs, PLDs. Yet other objects such as MEMs displays and flat panel displays can include repetitive regions.
Typically, ideally identical structural elements (referred to as cells) that are included within the same repetitive region are compared to each other or to a so-called “golden cell”. Both types of comparison are known as cell to cell comparison.
Memory arrays are often surrounded by non-repetitive regions. These non-repetitive regions are commonly compared to each other using a so-called die to die comparison.
Die to die comparison involves comparing image information of one die to image information of another die. It is known in the art that die to die comparison is significantly less sensitive to defects due to its reduced sensitivity in relation to cell to cell comparison. The latter has advantages over die to die comparison because it is less sensitive to process variations, color variations (a phenomena that occurs when bright field technology is applied and when a partially transparent layer is positioned above the cells), and to changes in the optical image acquisition (and/or illumination) process. These changes can include radiation intensity fluctuations, optics aberrations; focus related inaccuracies, sensor saturation, sensor array un-uniformity, misalignment, and the like.
Even cell to cell comparison has some disadvantages. It is responsive to differences between the acquisition of image information of cells that are close to the edges of the repetitive regions and the acquisition of image information of cells that are spaced apart from the edges of the repetitive regions. It is noted that image information of a certain structural element can be affected by the surrounding of that certain structural element due to relatively wide energy distribution of radiation that is used to illuminate the area and as a result of pattern information that passes through spatial filters when illuminating structural elements that are near the edge of the array. Typically, such spatial filters are adapted to block interference lobes of an array of repetitive structural elements. Non-repetitive regions can alter the location of the interference lobes thus pattern information can pass through these spatial filters.
FIG. 1 illustrates area 8 of a prior art wafer. Multiple memory cell arrays 10-18 are surrounded by vertical stitches (denoted V) and horizontal stitches (denoted “H stitch” 20-30). During a commonly implemented hybrid comparison process image information of repetitive structural elements within each array is compared to image information of repetitive structural elements within the same array while image information of vertical stitches are compared to image information of vertical stitches of another die. This hybrid comparison process suffers from the mentioned above drawbacks of die to die comparison and from the drawbacks of cell to cell comparison.
There is a growing need to provide improved systems, methods and computer program products that can evaluate an object.